1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device having a semiconductor chip and a multi-layered wiring member to which the semiconductor chip is connected. Further, the present invention is concerned with a method of producing such a semiconductor integrated circuit device.
Recently, electronic devices such as personal computers are oriented to down-sizing and high-speed operation (higher than 100 MHz). Under the above circumstance, it is necessary to improve the density of mounting electronic parts such as LSI (Large Scale Integrated Circuit) chips on a mounting board. In addition, it is required to improve the electric characteristics (for example, high-spewed operation performance) of semiconductor integrated circuit devices themselves. It is also desired to reduce the production cost of semiconductor integrated circuit devices. In short, it is desired to provide miniaturized, less-expensive semiconductor integrated circuit devices having excellent electric performance.
2. Description of the Prior Art
In order to improve the electric performance of semiconductor integrated circuit devices, it is usually attempted to reduce the length of wirings including bonding parts and increase the thickness thereof as much as possible and to employ a multi-layer structure in which signal lines are formed on layers different from layers on which power supply and ground lines are formed.
A flip-chip method is known as a bonding method having excellent electric performance. In the flip-chip method, a semiconductor chip is connected to a mounting board by means of bumps. More particularly, soldering bumps of a semi-spherical shape are formed on electrode pads formed on a semiconductor chip, and the semiconductor chip is connected to electrode parts formed on a chip mounting board. The above method is disclosed in, for example, "LSI HANDBOOK", edited by the Institute of Electronics and Communication Engineers and published by Ohm-sha, pp. 409-411). Another bump forming process used for the flip-chip method is known in which the ends of TAB (Tape Automated Bonding) leads are formed into a semi-spherical shape by punching using a metal mold (Japanese Laid-Open Patent Application No. 3-252148).
The multi-layering requires electric connections between layers. This is achieved by, for example, forming a series of holes in layers to be connected and plating the inner walls of the holes. Such holes are called via hole or through holes (see "PRINTED CIRCUIT BOARD TECHNICAL MANUAL", edited by Zaidan-Hojin, Hihon Purint Kairo Kogyokai, pp. 8-10).
However, the above bump forming methods are very complex and need high precision. Hence, the methods lead to increase in the production cost. The method of forming the via or through holes needed in the multi-layering is very complex, particularly, in the step of plating the holes or filling the holes with an electrically conductive material. This leads to increase in the production cost and decrease in the yield. Further, the via holes have a limited arrangement pitch due to the mechanical strength of the board and formability, and thus cannot be arranged finely.